Description ¡El NB100LVEP224 is a low skew 1-to-24 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. ¡El part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. ¡El two clock inputs are differential ECL/PECL and they are selected by the CLK_SEL pin. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE) is synchronous ensuring the outputs will only be enabled/disabled when they are already in LOW state (See Figure 4). ¡El NB100LVEP224 guarantees low output-to-output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. In any differential output, the same bias and termination scheme is required. Unused output pairs should be left unterminated (open) to “reduce power and switching noise as much as possible.” Any unused single line of a differential pair should be terminated the same as the used line to maintain balanced loads on the differential driver outputs. ¡El wide VIHCMR specification allows both pair of CLOCK inputs to accept LVDS levels. ¡El NB100LVEP224, as with most other ECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the LVEP224 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. Single-ended CLK input operation is limited to a VCC ≥ 3.0 V in LVPECL mode, or VEE ≤ -3.0 V in NECL mode. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on PECL terminations, designers should refer to Application Note AND8020/D.